In general, a semiconductor memory circuit typically consists of an array of rows and columns. Each intersection of a row and column defines a memory “cell” that stores either a binary logic “1” or a “0”.
There are many types of memory available for various storage applications. For retrieval processing of large amounts of data, an associative memory called Content Addressable Memory (CAM) is gaining widespread use in a variety of applications including data networking. The important feature of CAM is that it can perform a search and compare operation between specified user data and stored data and return match or mismatch results.
CAM arrays are also made up of intersections of rows and columns of CAM cells, as with most typical memories. In addition to rows and columns of cells, associated with each row of CAM cells is a matchline and a matchline detection circuit or sense amplifier that senses the changes in the logic state of a matchline for the cells in that row. The matchline sense amplifier detects a match or a mismatch during a CAM search and compare operation. FIG. 4 illustrates a block diagram of a typical array of memory cells where the detection circuit DC is used to sense a match or mismatch on the matchline ML connected to a row of several CAM cells.
Conventionally, during matchline sensing, there is no reference level available to compare a matchline to be sensed, the selected matchline ML either remains at a precharged voltage (VDD, for example) for a match detection, or discharges (towards ground voltage VSS, for example) for a mismatch detection. A match or mismatch condition must be detected for each cell in a bit search operation, and every matchline ML must be sensed simultaneously with typically 32,000 other matchlines or more. Since matchlines typically discharge from to precharged voltage in the case of a mismatch in any bit, and statistically, mismatches are much more frequent than matches, dynamic power due to matchlines switching simultaneously becomes a significant factor in designing the CAM which has to be accounted for.
Moreover, in high-density memory systems where the number of CAM cells in each row can reach 128 or higher, the speed for discharging a matchline is virtually limited by the capacitance of the matchline. This inherent discharge limitation cannot cope with the fast switching speed of high-density CAM systems where the search cycle time is of the order of 15 ns.
A sensing scheme is therefore required that will limit the matchline voltage swing in order to reduce the dynamic power of sensing all the matchlines while allowing for high speed search operations under low power consumption.
There are several known approaches to design match/mismatch detection circuits. FIG. 1 shows a prior art example for sensing a matchline as disclosed in U.S. Pat. No. 5,051,948 by Watabe et al. In this sensing scheme, a current-voltage conversion circuit is first used to convert the matchline current into a voltage value. This voltage is the sensed by a voltage sensing circuit using a dummy reference voltage. This design may not be suitable for high-density CAM systems for the following reasons:                a. the current to voltage conversion is performed by a CMOS inverter that is biased as an analog amplifier. Under this arrangement, DC power is constantly consumed during entire operation and such consumption of power would be well beyond the limits that a high-density integrated circuit package could handle;        b. The dummy reference voltage circuit also uses CMOS inverters as an analog amplifier. This scheme not only consumes DC power but also precludes the appropriate tracking of the reference voltage with that of the matchline under high-speed, high-density memory sensing conditions; and        c. The circuit blocks of this type of design consume a considerable amount of integrated circuit area.In summary, the inhibiting characteristic of this prior art design, when applied to high-density CAM systems, are both power and area consumption.        
FIG. 2 shows a second prior art circuit, as disclosed in U.S. Pat. No. 5,012,448, utilized in a Read-only-Memory (ROM) multilevel memory. This sensing scheme incorporates two CMOS inverters that operate as small-signal amplifiers each connected to NMOS devices for current sensing. The sources of both the reference side NMOS and the matchline side NMOS are fed into a current mirror circuit. As in the first prior art discussed, this second prior art approach may not be suitable for high-density memory applications because of the unacceptably large dissipation of power. In addition, due to the current mirror arrangement, a full CMOS level swing cannot be efficiently achieved.
A third prior art design is disclosed in U.S. Pat. No. 4,763,026 for single-ended data sensing. As illustrated in FIG. 3, this approach generates a reference voltage from the dateline itself. However, a key disadvantage of this prior art approach is that the reference node VREF is allowed to float after being precharged. Based on the high capacitive load TI4, the precharged voltage value of VREF is expected to remain at the same level during the sensing operation. The reliance on a high capacitive load to hold the precharged value of the reference node may not be appropriate because, in a VLSI interchip environment, high noise injections from high speed operations can corrupt the value of the capacitive load and cause an unintended reversal in operation. A second disadvantage of this prior art design is that such a large dummy capacitance requires an appreciably large area on the VLSI chip. This may be cumbersome and impractical for a high-density CAM arrangement where 32,000 or more matchline sense amplifiers are required.
In summary, there is clearly a need for matchline sense amplifiers that are capable of                quickly sensing a (highly capacitive) matchline;        limiting the matchline swing; and        sense all matchlines simultaneously (32K and above),but in a manner which reduces the portion of integrated chip area used for high-density memory applications and reduces heat dissipation.        